RESEARCH

Welcome to my research page! Here is a detailed overview of my work in the fields of electrical testing, device characterization, process flow optimization, and circuit simulation.

Electrical Testing and Device Characterization

My research focuses on the advancement of emerging non-volatile memory technologies, with a strong emphasis on both thin-film Charge-Trap Flash and Resistive Random Access Memory (ReRAM) devices. Utilizing semiconductor parameter analyzers such as the Keithley 4200A-SCS system and Lakeshore Cryotronics system, I have conducted comprehensive electrical testing, including:

CV (Capacitance-Voltage), IV (Current-Voltage), and Frequency-Varying Sweeps: These measurements help analyze the electrical behavior and performance of novel memory devices.
Pulse-Based Programming and Erasing Techniques: Implemented techniques to enable precise control over data retention and endurance, which are essential for evaluating the long-term reliability of memory devices.
Endurance and Retention Testing: Carried out aging tests across a wide temperature range (130K to 398K) to assess the stability and performance of devices over time.

Through automated data analysis using Python scripts, I have efficiently organized and extrapolated experimental data, fitting it to device physics equations for a deeper understanding of underlying conduction mechanisms.

Process Flow Optimization and Device Fabrication

In the area of process flow development and fabrication, I have been actively involved in designing and optimizing devices through various fabrication techniques:

Forming-Free TaOx-Based ReRAM Devices: Utilizing Physical Vapor Deposition (PVD) and high-temperature reactive sputtering with Ta and O₂, I have developed robust devices verified by Scanning Electron Microscopy (SEM). My optimized device stacks feature high ON/OFF ratios (> 1000) and low operating voltages (< 3V), enabling reliable multi-state switching.
Advanced Device Integration: Collaborated with Penn State’s Materials and Life Sciences departments to integrate Organic Hybrid Perovskite (OHP) materials for next-generation ReRAM devices. This partnership has led to the development of CMOS-compatible OHP-DNA ReRAM processes featuring SiO₂ wall formation, enhancing device stability.
Wet Etching and Photolithography: Implemented wet etching processes for precise metal and insulator patterning, alongside top electrode photolithography on 4-inch Si wafers, optimizing device areas ranging from 30–150 µm².

Circuit Simulation

My work extends into the design of efficient read-write circuitry for ReRAM crossbars using a 1 Transistor - 1 Resistor (1T-1R) configuration. I utilize NCSU FreePDK45 for circuit design, incorporating:

Voltage Latched Sense Amplifiers: To enhance data sensing and reading accuracy.
Row-Column Decoders: For efficient data access and memory management.

Equipment and Cleanroom Expertise

My research is supported by extensive use of advanced equipment, including:

Keithley 4200-SCS Parameter Analyzer for detailed electrical characterization.
Cascade Probe Station and Lakeshore Cryotronics Cryogenic Probe Station for testing at various temperatures.
AJA Orion Sputtering System, March CS-1701 RIE, and Nanonex NX-2600 Lithography for device fabrication and patterning.

In addition, I have significant cleanroom experience with tasks such as wafer cleaning, oxidation, reactive ion etching (RIE), physical vapor deposition (PVD), and photolithography.

Publications and Conferences

Electrical Characterization and Analysis of Ultra-Thin Film HfO2/MgO Oxides for High-Density Charge Trap Flash Memory: In progress
CMOS BEOL-Compatible TaOx-Based ReRAM Devices for Emerging Memory Applications: In progress
• A study on Bio-inspired synergistic effect through DNA Incorporation in 2D Perovskites for Next- Generation RRAM devices: Presented at the MRS Fall 2024 Conference.